GC64-ISA-Sim


Overview

The GC64-ISA-Sim is a clone of the RISCV ISA Sim, code named “Spike.”  We have branched the core RISCV Spike source in order to extend it in the following ways:

  • Adding the necessary instruction extensions for the GC64 RISCV extension (in progress)
  • Adding support for software-managed scratchpad memories mapped into the proper virtual address spaces
  • Adding support for MMU-level memory tracing (all load and store requests produce trace output).

Obtaining the Source

The source for GC64-isa-sim can be obtained via the GC64 git repository as follows:

$> git clone http://discl.cs.ttu.edu/gitlab/gc64/gc64-isa-sim.git

Building GC64-ISA-Sim

The GC64-isa-sim is built in the same manner as the original Spike simulator (See the original RISCV build instructions here).  We assume that you have the RISCV-tools built and installed as well as the $RISCV environment variable set to the installation directory.  The resulting “spike” binaries will be created in the same manner as the original riscv-isa-sim build.

$> cd gc64-isa-sim
$> mkdir build
$> ../configure --prefix=$RISCV --with-fesvr=$RISCV
$> make
$> make install

GC64-ISA-Sim Extensions

The GC64-ISA-Sim currently adds two additional options to the spike execution environment.  The spike options are listed as follows:

$> $RISCV/bin/spike -h

usage: spike [host options] <target program> [target options]
Host Options:
-p <n>             Simulate <n> processors
-m <n>             Provide <n> MB of target memory
-d                 Interactive debug mode
-g                 Track histogram of PCs
-s <n bytes>       Initiate N-byte scratchpad memory
-h                 Print this help message
-t                 Enable memory tracing
–ic=<S>:<W>:<B>   Instantiate a cache model with S sets,
–dc=<S>:<W>:<B>     W ways, and B-byte blocks (with S and
–l2=<S>:<W>:<B>     B both powers of 2).
–extension=<name> Specify RoCC Extension
–extlib=<name>    Shared library to load

Note the ‘-s’ and ‘-t’ options.  The -s option creates an N-byte software-managed scratchpad memory for each new processor.  In the future, we will add options to explicitly outline the distribution of processors to scratchpad memories (thus simulating a GC64 socket architecture).  By default, the scratchpad is allocated using 20,000,000 bytes at base virtual address 0x0000000080000000.  The size of the scratchpad can be modified using the -s option.  We describe how to modify the base virtual address in the next section.  In the GC64 spike simulator, memory can be explicitly read from and written to using the virtual address range {base, base+N-bytes}.

In addition to the scratchpad memory support, we also add explicit memory tracing capabilities.  All load and store requests to the MMU (via the virtual memory translation logic) are output to the console.  Note that this can become EXTREMELY verbose.  Also note that the loads and stores output in the trace logs also include ICACHE and DCACHE fill requests, respectively.  The log output is formatted as follows:

REQUEST_TYPE:REQUEST_SIZE_IN_BYTES:REQUESTING_PROC_ID:ADDRESS

where,

  • REQUEST_TYPE is WR (write) or RD (read)
  • REQUEST_SIZE_IN_BYTES is the number of bytes to read or write
  • REQUESTING_PROC_ID is the CPU ID of the requesting CPU.
  • ADDRESS: 64-bit virtual address of the request

An example trace is as follows:

R:1:0:0x000000000002028e
RD:4:0:0x000000000001c75c
RD:8:0:0x000000000001c750
WR:4:0:0x000000000001c75c

 

Modifying the Base Scratchpad Address

Some users or developers may wish to modify the base virtual address containing the scratchpad memory.  Warning!  You may do this at your own risk!  All other tools will likely need to be modified in order to sufficiently support this.  Despite this, you may modify this value by adding the following to the build process (note we use 0x0000000060000000 as the new base virtual address):

$> export CFLAGS=-DGC64_BASE_ADDR=0x0000000060000000
$> export CXXFLAGS=$CFLAGS
$> ../configure --prefix=$RISCV --with-fesvr=$RISCV
$> make
$> make install