Overview


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The GoblinCore64 (herein referred to as GC64) that was originally designed to facilitate the construction of a high performance core architecture that was well- suited to executing applications traditionally known as ”data intensive.” These applications generally refer to algorithms that operate on sparse data structures such as graphs, sparse matrices and/or perform nonlinear combinatorial operations (et.al.). We consider all of the aforementioned target application areas to share the following two general characteristics.

  • Non-Unit Stride: All of the applications we consider as design targets for GC64 perform a disproportionate number of non-unit stride computa- tions. These computations may simply be non-unit stride, scatters, gath- ers or completely random. In all cases, the data elements are not generally well-suited to traditional long SIMD or data caching architectures.
  • Memory Intensive: Given the first characteristic, we also assume a la- tent characteristic with respect to the memory bandwidth requirements. Given the sparsity or non-linear access requirements, we assume that the design targets operate with a disproportionally high bandwidth to compute ratio. As such, we consider them to be memory intensive rather than computationally intensive.

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In addition to the core design requirements, we also sought to build a completely open source architecture and tool chain suitable for architectural research in academia and possible commercial implementations. As such, we sought to build BSD-like licensing around the core ISA, simulation infrastructure, tools and toolchain. Given this, we found that our implementation goals aligned well with the RISC-V project. These include, but are not limited to the following:

  • A completely open ISA that is freely available to academia and industry.
  • An ISA separated into a small base integer ISA.
  • Support for the revised 2008 IEEE-754 floating-point standard.
  • An ISA with native support for highly-parallel multicore or many core implementations.

In addition to the core RISC-V goals, we also wanted to achieve the following architectural goals (as related to our target design requirements):

  • Provide simple architectural structures that are conducive to constructing highly (MIMD) parallel and concurrent applications
  • Provide simple ISA extensions conducive to compiler optimization of con- current applications
  • Provide a low-level, mutable parallel construct in hardware that can be easily mapped to higher level parallel programming models (threads, tasks, etc)
  • Provide hardware mechanisms to minimize context switch latency to a very small number of cycles (goal of single cycle context switching events)
  • Provide a well-defined mechanism when context switch events occur
  • Provide a well-defined mechanism for user applications to explicitly induce context switch events

The GoblinCore64 project is sponsored by the Data Intensive Scalable Computing Laboratory in the Department of Computer Science at Texas Tech University.

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